Basic Speed and Power Properties of Digital Floating-Gate Circuits Operating in Subthreshold

For digital circuits with ultra-low power consumption, floating-gate circuits have been considered to be a technique potentially better than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper the basic performance related properties such as power, delay, power-delay product (PDP), and energy-delay product (EDP) for floating-gate circuits operating in subthreshold are investigated. Based on circuit simulations in a 120nm process technology, it is shown that for the best case, the power can be reduced approximately by one order of magnitude at the expense of increased delay, while the PDP is more or less constant in comparison to static CMOS. The EDP can be reduced by two orders of magnitude at the expense of reduced noise margins.